Abstract: In this thesis it is demonstrated that reasonably efficient delay insensity circuits can be automatically synthesized from high-level specifications. The language ``Synchronized Transitions'' is used for specification of the circuits. Two methods to synthesize a specification are presented and implemented in two compilers. Using the compilers, a Synchronized Transition specification can be transformed to a netlist. For transformation from a netlist to a layout, a commercial design system is used (Solo-1400 from ES2). No manual intervention is necessary when a specification is translated into layout. Hazards and timing problems are examined and eliminated, where present, in the synthesized circuitry. Layouts synthesized using the compilers are compared with layouts made by hand. With the most efficient of the two methods of synthesis, a 8900 transistor chip has been synthesized directly from a 620 line specification. This layout is three times larger than an equivalent full custom layout constructed by hand.

One-line summary: Fully automatic translation of a software program to a hardware layout of a corresponding delay-insensitive chip.

Back to Per's publication page.